This invention pertains to a method for manufacturing integrated circuits. In DE-OS No. 30 09 434 a process is described for manufacturing a monolithic integrated circuit comprising at least one bipolar planar transistor whose emitter region is formed in one surface side of a semiconducting substrate into the base region, which is diffused into the collector region. For manufacturing an integrated bipolar transistor without epitaxy, five photoresist masks are required which are used to manufacture firstly the collector region, secondly the base region, thirdly the emitter region, fourthly the contact holes and fifthly the interconnection pattern. In this process, by employing a first photoresist mask, the collector region is first of all restricted. The dopings of the collector region are implanted in this region and diffused thereafter. Then, by employing a second photoresist mask, the base region is restricted and the dopings of the base region are implanted. Following this, the dopings of the emitter region are implanted into the emitter area. Finally, by employing one photoresist mask, contact holes are produced in the insulating layer covering the surface side and an interconnection pattern is produced on the insulating layer, for contacting the regions.
A considerable proportion of the defect rates in the manufacture of monolithic integrated solid-state circuits are caused by faults during the photoresist processes. Moreover, the manufacturing costs are determined by the number of processes and defect rates. Therefore, it is of great advantage to keep the number of photoresist processes as small as possible, so that apart from an increased yield, it becomes possible to reduce the structures in size and, consequently, to achieve a higher integration density.